1. Field of the Invention
The present invention generally relates to a circuit board process, and more particularly, to a circuit board process with embedded circuit.
2. Description of Related Art
In recent years, along with the rapid advancement of fabrication techniques in electronic industry, circuit boards can be designed for carrying various small-volume electronic components to be applied to various electronic products. FIGS. 1A˜1H are cross-sectional views illustrating a conventional circuit board process. The conventional circuit board process includes following steps. First, as shown in FIG. 1A, a laminate 110 is provided, wherein the laminate 110 has a core layer 112 and a copper foil layer 114 on each side of the core layer 112. Next, as shown in FIG. 1B, a patterning process is performed to the copper foil layer 114 on each side of the core layer 112 to form a first circuit layer 114′ respectively. Thereafter, as shown in FIGS. 1C˜1D, a dielectric layer 120 and a copper foil 130 are laminated on each side of the laminate 110, wherein the dielectric layer 120 is laminated between the core layer 112 and the copper foil 130.
After laminating the dielectric layer 120 and the copper foil 130 on each side of the core layer 112, an opening 140 is formed on the copper foil layer 130 at each side of the core layer 112 to expose a portion of the dielectric layer 120, as shown in FIG. 1E. Thereafter, as shown in FIG. 1F, the dielectric layer 120 exposed by the openings 140 is removed to form another opening 150 for exposing the first circuit layer 114′. Thereafter, as shown in FIG. 1G, plating copper is filled into the opening 150 and the opening 140 through an electroplating process to form a conductive hole 160. Next, as shown in FIG. 1H, a photolithography process is performed on a portion of the plating copper in the copper foil layer 130 and the conductive hole 160 to form a second circuit layer 130′ on the dielectric layer 120. Thus, the fabrication of the circuit board 100 is completed, and the second circuit layer 130′ may be electrically connected to the first circuit layer 114′ through the conductive hole 160.
It shall be noted that in the conventional technique described above, the disposition of the conductive hole 160 and the second circuit layer 130′ are defined in different steps. To be specific, an alignment process is first performed while fabricating the conductive hole 160 in order to form the conductive hole 160 at a predetermined position, and another alignment process has to be performed while fabricating the second circuit layer 130′ in order to form the second circuit layer 130′ at a predetermined position. Thus, the conventional technique requires several alignment processes for defining the dispositions of the conductive hole 160 and the second circuit layer 130′, which reduces circuit fabrication efficiency on the circuit board. Besides, since the conductive hole 160 and the second circuit layer 130′ are defined on the circuit board 100 respectively through different alignment processes, the conductive hole 160 and the second circuit layer 130′ may not be defined accurately at predetermined dispositions thereof under the affection of the process tolerance, therefore the alignment accuracy of the circuit on the conventional circuit board is reduced greatly.
On the other hand, in a circuit board fabricated by the conventional technique, there is only one contact surface between the circuit layer and the dielectric layer, therefore the circuit layer and the dielectric layer may not be bonded tightly and accordingly the reliability of the circuit on the circuit board may be adversely affected.